A plasma display panel (PDP) display device includes a PDP unit being composed of a thin front glass panel and a thin back glass panel arranged facing each other via a plurality of barrier ribs, having fluorescent layers of each of the colors red (R), green (G), and blue (B) applied between the barrier ribs, and discharge gas enclosed in a discharge space which is a gap between the two glass panels. A plurality of pairs of display electrodes, each pair consisting of a scan electrode and a sustain electrode, are formed on the front glass panel. Also, a plurality of address electrodes are aligned on the back glass panel, so as to be perpendicular to the display electrodes, the discharge space being between the address electrodes and display electrodes. In a subfield (which is described later), each of the electrodes is applied with pulses such as initialization pulses, scan pulses, write pulses, sustain pulses, and erase pulses, based on, for example, the drive waveform process shown in FIG. 15, so that fluorescent light is emitted according to the electric discharge generated in the discharge gas. A PDP display device having this kind of construction is superior to a conventional CRT display in that it does not involve problems including limitations in viewing angles and increased depth and weight when a large screen PDP is produced, as a large screen conventional display CRT does.
There is much demand for this kind of large screen, high definition PDP display device, and at present PDP display devices of 50 inches or more in size are being commercially produced.
Note that when a television video is shown on a display using an analog color television video signal system, one second of an image is constructed from 60 frames (or fields). In a basic PDP display device, because image display is basically possible only by illumination and extinction, a method for displaying halftones is used in which the illumination time corresponding to each of the colors red (R), green (G) and blue (B) is time-shared, as shown in the frame structure diagram FIG. 16. For example a plurality of level gradation display times are in accordance with a combination of eight subfields which constitute 1 (TV) frame. The relative luminance ratios of each of the eight subfields are assigned, in ascending order, binary weights such as 1, 2, 4, 8, 16, 32, 64, 128, and display, for example, a total of 256 gradations (level 0 gradation to level 255 gradation) according to a combination of the different weights of the 8 bit relative luminance ratio. Further, in order to maintain a sufficient brightness during actual operation, a number of sustain pulses to be applied during the discharge sustain period of each subfield is substantially set in proportion with the assigned weight. It is supposed that the number of pulses, in the described relative luminance ratio order is 3, 7, 15, 31, 63, 127, 255, 511 (wherein “level 0 gradation”, “level 1 gradation”, “level 2 gradation” to “level 8 gradation” and so on, which are described later, show specific level gradations included in 256 total gradations).
A PDP display device having the above characteristics incurs the following problems during low-level gradation display.
Namely, in display it is generally desirable that the relative luminance ratio decreases as the gradation level of the display becomes lower, as this allows dark gradation display to be expressed smoothly. When using a CRT to display, of the total 256 gradations, level 0 gradation, and level 1 gradation which has a relative luminance ratio corresponding to the smallest weight, the luminance ratio showing the difference in gradation level is close to 0 cd/m2, and a smooth gradation display time is possible. However in a PDP display device, the luminance ratio of level 0 gradation and level 1 gradation is no less than 2 cd/m2, therefore it is difficult to display such a change in luminance as smoothly as in a CRT device.
In response to this problem, if the sustain pulse rate is set at a very low gradation setting, light emission gained by sustain pulses during the level 1 gradation display time can be restricted, however because light emission is left over from the initialization pulse, write pulse, and erase pulse, luminance cannot be substantially lowered. Further, even if gradation display time is falsely attempted using error diffusion processing (dither method), error diffusion noise is noticeable on the screen because the gradation level is low, and rather than an effective error diffusion result being gained, a new problem of deterioration in picture quality arises.